The present invention generally relates to processing low k materials on a semiconductor substrate. In particular, the present invention relates to methods of making and chemical mechanical polishing a low k material layer containing a high modulus filler.
High performance integrated circuit chips contain of millions of transistors that perform various functions including random access memory, central processing communications, and the like. Each of the transistors is interconnected with electrically conducting elements. In order to efficiently accomplish this on a single chip, a typical integrated circuit chip contains multiple layers of conducting elements. Since there are size constraints associated with placing millions of conducting elements on a chip having an area of only a few square centimeters, the connecting elements themselves are very small, and the distance that separates conducting elements is small as well.
Dielectric materials are widely used in the semiconductor industry to separate structures on an integrated circuit chip, such as separating metal interconnect layers from active devices. Dielectrics are also used to separate two adjacent metal interconnect layers to prevent shorting between the metal layers. With an increasing number of levels in integrated circuit chips, there is growing emphasis on the quality of so-called interlevel dielectrics. This is because multiple levels of metal interconnects are necessary in order to achieve higher packing densities and smaller chip sizes with increased circuit complexity.
The smaller geometries raise certain electrical performance problems that are not of concern in older generation integrated circuits. The reduced spacing results in increased electrical capacitance, which in turn causes capacitative interconnect delay that can slow down the operational speed of the circuit. Increased capacitance increases the amount of power that the integrated circuit requires to operate. Increased capacitance also causes cross-talk that can result in generating signal errors.
Since the dimensions of current integrated circuits are constrained, and since the trend is to continue decreasing geometries, it is necessary to reduce the capacitance in integrated circuit chips. Conventional semiconductor fabrication commonly uses high density or conventional silicon dioxide and/or spin-on glass as a dielectric.
One disadvantage associated with high density silicon dioxide and/or spin-on glass dielectrics is their relatively high permitivity or dielectric constant. Typically, high density silicon dioxide and/or spin-on glass have a relative (to permitivity of free space) dielectric constant of 3.9 or higher. High dielectric constant materials produce capacitive loads on the adjacent conductors which degrades performance of both high frequency and high density transistors.
Another disadvantage associated with high density silicon dioxide and/or spin-on glass dielectrics is that thicker dielectric layers are required to compensate for the high dielectric constant. Thicker layers result in larger geometry devices, increasing the overall size and cost of the integrated circuit chip while reducing functionality. Additionally, thick dielectric layers increase planarization problems, making it difficult to form multi-layer metallizations on top of the dielectrics.
Generally speaking, therefore, it is desirable to provide a dielectric material layer with a high breakdown field strength and low leakage current. Low k material layers are attractive in this respect because they possess both high breakdown field strength and low leakage current. However, there are problems associated with forming low k material layers. For instance, heat causes deleterious structural damage to a low k material layer or film (structural collapse of the low k material). Temperatures as low as 350xc2x0 C. can cause such damage in certain low k material layers. This is a problem because semiconductor processing often involves high temperature steps. Consequently, various layers used in fabricating semiconductor devices must be able to withstand high temperatures.
Another problem associated with low k material layers involves lack of structural integrity or lack of mechanical strength. This deficiency limits the extend to which further processing can be employed with low k material layers. For example, although chemical mechanical polishing (CMP) techniques are widely used in semiconductor fabrication, CMP techniques are not typically used to process low k material layers due to the lack in hardness.
The present invention provides methods for making semiconductor structures with improved low k insulation materials. The present invention also provides methods for forming high quality low k material layers in semiconductor structures by using a combination of a low k polymer material and a high modulus filler. The high quality low k material layers leads to the formation of electronic devices having desirable electrical properties. The low k material layers made in accordance with the present invention have at least one of high mechanical strength, high temperature stability, the absence of residual solvent, a desirable structural network, high breakdown field strength and low leakage current.
One aspect of the present invention relates to a method processing a low k material involving providing a low k material layer comprising one or more low k polymer materials and one or more high modulus fillers on a semiconductor substrate, and chemical mechanical polishing the low k material layer so as to remove a portion of the low k material layer from the semiconductor substrate without substantially damaging unremoved portions of the low k material layer.
Another aspect the present invention relates to low k material layers for a semiconductor structure containing one or more low k polymer materials and one or more high modulus fillers, as well as methods of making the low k material layers.